From bare die to finished package. Complete backend semiconductor services: wafer dicing, die attach, wire bonding, flip chip, molding, ball attach, marking, testing, and tape & reel.
Every package type is supported by documented process flows, statistical process control, and JEDEC-standard qualification protocols. Engineering support from feasibility review through qualification.
Controlled collapse chip connection (C4) technology using solder bumps or Cu pillar interconnects. Active face of the die faces the substrate for shortest possible electrical path and superior thermal performance. Capillary underfill or pre-applied underfill processes available.
| Parameter | Capability |
|---|---|
| Min Bump Pitch | 130 µm (Cu pillar) |
| Max Ball Count | 2,500+ |
| Min Ball Pitch | 0.3 mm |
| Max Body Size | 55 x 55 mm |
| Substrate | BT / ABF / MCE (14L max) |
| Underfill | Capillary / NCF / NCP |
| Die Thickness | ≥50 µm |
| Thermal Solution | Lid / TIM / Exposed die |
Fan-in and fan-out wafer-level chip scale packaging. Redistribution layer (RDL) routes I/O pads to a larger array of solder balls. True chip-scale: package footprint equals or minimally exceeds die size. Wafer-level processing for cost efficiency at volume.
| Parameter | Capability |
|---|---|
| Type | Fan-In / Fan-Out |
| Min Ball Pitch | 0.35 mm |
| Max Die Size | 5 x 5 mm |
| RDL L/S | 10/10 µm |
| Ball Metallurgy | SAC305 / SAC405 |
| Wafer Size | 200 mm / 300 mm |
| Passivation | PI / PBO / BCB |
| Backside Coating | Available (light shield) |
Direct die attach onto PCB or flexible substrate. Wire bonding from die pads to substrate pads. Black epoxy glob-top encapsulation for mechanical and environmental protection. Cost-optimized for high-volume consumer, LED, and sensor applications.
| Parameter | Capability |
|---|---|
| Wire Type | Au / Cu / PdCu (18-25 µm) |
| Min Bond Pad Pitch | 35 µm |
| Bond Method | Thermosonic ball-wedge |
| Substrate | FR4 / Flex / Ceramic / MCPCB |
| Encapsulation | Glob-top / Dam-and-fill |
| Max Wire Length | 5 mm |
| Loop Height | ≤150 µm |
Multi-die, multi-technology integration in a single package. Combines logic, memory, passives, and shielded sections in one form factor. Ideal for RF front-end modules, IoT controllers, and wearable systems requiring minimal PCB area.
| Parameter | Capability |
|---|---|
| Max Die Count | 12 per package |
| Min Passive Size | 01005 (0.4 x 0.2 mm) |
| Interconnect | Wire bond / RDL / Embedded |
| Shielding | Conformal / Compartment |
| Substrate | LTCC / Laminate / Leadframe |
| Package Height | ≤1.0 mm (ultra-thin) |
| Test | RF parametric / Functional |
Vertical stacking of packaged devices for memory-on-logic or logic-on-logic configurations. Precision placement with controlled z-height, solder paste dipping, and reflow profile optimization. Critical for mobile application processors with LPDDR memory.
| Parameter | Capability |
|---|---|
| Max Stack Height | 4 layers |
| Package Thickness | ≤1.0 mm total |
| Warpage Control | ≤80 µm (Shadow Moire) |
| Placement Accuracy | ±15 µm |
| Interconnect | TMV / Edge bond / Solder ball |
| Bottom Pitch | ≥0.4 mm |
Complete range of mainstream package formats. Plastic BGA (PBGA), ceramic BGA (CBGA), and tape BGA (TBGA). Punched and sawn QFN with exposed pad options. LQFP and TQFP with standard and fine pitch. Leaded and lead-free finish options.
| Parameter | Capability |
|---|---|
| QFN Pitch (min) | 0.35 mm |
| QFP Pitch (min) | 0.4 mm |
| BGA Ball Pitch (min) | 0.5 mm (standard) |
| Lead Finish | Sn / NiPdAu / Matte Sn |
| Mold Compound | Epoxy / Green / Halogen-free |
| Marking | Laser / Ink |
| Singulation | Saw / Punch / Laser |
Micro-electromechanical systems packaging with cavity and open-cavity solutions. Hermetic sealing options, getter integration for vacuum maintenance, and stress-isolation mounting structures. Compatible with inertial, pressure, acoustic, and optical MEMS devices.
| Parameter | Capability |
|---|---|
| Cavity Type | Open / Sealed / Getter-integrated |
| Hermeticity | ≤5 x 10-8 atm·cc/s He |
| Lid Material | Kovar / Ceramic / Glass / Si |
| Die Attach | Soft / Hard / Eutectic / Glass frit |
| Wire Bond | Au / Al wedge bonding |
| Get Deposition | Thin-film / Pill / Printed |
Full-spectrum test services from wafer probe through system-level functional test. Custom load board design, test program development, and ATE platform coverage.
Pre-dicing electrical test at wafer level. Probe card design and fabrication. Parametric and functional test patterns. Inkless mapping to known-good-die database. Temperature range: -40 to +150°C.
Post-packaging electrical verification. Full DC, AC parametric, and functional test. Multi-site parallel test for throughput. Handler: pick-and-place, gravity, turret.
Accelerated life test per JESD22-A108. Dynamic and static burn-in. Ambient and junction temperature monitoring. Up to 1,000 hours. Post-burn-in electrical verification.
Application-like test environment on custom PCB. Corner-case and margin testing. Protocol-aware testing for SerDes, DDR, PCIe interfaces. Real-time parametric logging.
Temperature cycling (TC), thermal shock (TS), HAST, autoclave, unbiased HAST per JESD22. Solderability, bend test, drop test. Full JEDEC qualification suite.
X-ray (2D/3D CT), CSAM, cross-section, SEM/EDX, decapsulation, emission microscopy. Root cause analysis and corrective action reporting.
Share your device specifications — die size, pad count, pitch, thermal requirements, and target volume. We return a complete technical proposal with process flow within 24 hours.