EMS-IC Semiconductor Packaging and Testing Facility

Shenzhen Semiconductor Cluster

Silicon Perfected

Advanced IC packaging, assembly, and testing — from engineering samples to volume production. JEDEC-compliant, ISO-certified.

Submit Package Drawing Capability Statement

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Core Capabilities

IC Packaging & Assembly Services

From single-die wire bond to advanced 2.5D/3D heterogeneous integration. Every package type backed by in-house process engineering and JEDEC-standard qualification.

Flip Chip BGA

Controlled collapse chip connection with underfill. Fine-pitch Cu pillar and solder bump technologies for high-density interconnect.

Pitch: ≤0.3mm Balls: ≤2,500

Wafer-Level CSP

Fan-in and fan-out wafer-level chip scale packaging. Redistribution layer (RDL) technology for the smallest possible footprint.

Pitch: ≤0.35mm Die: ≤5x5mm

COB / COF

Chip-on-board and chip-on-flex assembly. Direct die attach with wire bonding. Black epoxy glob-top encapsulation for cost-sensitive applications.

Wire: Au/Cu ≤18µm Pads: ≤45µm

SIP Module

System-in-package integration. Multi-die, passive component embedding, and shielded module assembly for RF, IoT, and wearable applications.

Dies: ≤12/package Passives: 01005

POP Stacking

Package-on-package stacking for memory-on-logic configurations. Precision placement with controlled standoff height and warpage management.

Stack: ≤4 layers Height: ≤1.0mm

BGA / QFN / QFP

Full range of mainstream package types. PBGA, CBGA, TBGA, QFN (punched/sawn), LQFP/TQFP. Standard and custom leadframe options.

QFN: ≤0.35mm pitch BGA: ≤55mm body

MEMS Packaging

Micro-electromechanical systems packaging with cavity and open-cavity solutions. Hermetic sealing, getter integration, and stress-isolation mounting.

Cavity: Custom Leak: ≤5x10^-8

Testing & Burn-In

Wafer probe, final test, system-level test, and HTOL burn-in. Custom load boards, test program development, and full ATE capability.

Temp: -55 to +175°C Pins: ≤2,048

Manufacturing Precision

Technical Specifications

Our Shenzhen facility operates at the frontier of assembly capability. Every parameter verified through statistical process control.

01005

Minimum Component Size

0.4mm x 0.2mm passive component handling on high-speed placement systems

0.3mm

Minimum BGA Pitch

Fine-pitch ball grid array with automated optical inspection at every step

X-Ray

Inline Inspection

2D and 3D (CT) X-ray for void detection, wire sweep analysis, and solder joint integrity

Class 1K

Cleanroom Rating

ISO Class 6 (Fed Std 209E Class 1,000) for die attach and wire bond operations

JEDEC

Standards Compliance

JESD22 reliability test methods, J-STD-020 MSL classification, IPC-A-610 Class 3

SPC

Process Control

Real-time statistical process control with CpK ≥ 1.67 across all critical parameters

Process Window

Parameter	Capability	Standard
Max Package Body Size	55 x 55 mm	JEDEC MO-xxx
Min BGA Ball Pitch	0.3 mm	IPC-7095
Max Ball Count	2,500+	Depopulated array
Wire Bond Pitch	35 µm	Au/Cu/PdCu wire
Flip Chip Bump Pitch	130 µm	Cu pillar + SAC cap
Die Thickness (min)	50 µm	DBG process
Substrate Layer Count	Up to 14L	BT / ABF / MCE
Underfill Gap	15 µm	Capillary / NCF
MSL Rating	Level 1-6	J-STD-020
Test Temperature Range	-55 to +175 °C	JESD22-A104

Next Step

Ready to Package Your Silicon

Send your package drawing or requirements. Our applications engineering team responds with a technical proposal within 24 hours — including process flow, timeline, and NRE estimate.

Submit Package Drawing Request Capability Statement